Pure deposition or layer production of group III nitride layers on silicon wafers, in particular in a (111) orientation using buffer layers, is disclosed in DE 102 06 750 A1, DE 102 19 223 A1 and WO 2008/132204 A2. This involves deposition over the whole surface, without any structuring and without exposing the original Si surface. The major challenge of the method is to minimise the layer interlocking, based on the different lattice constants and lattice structure, by using adapted buffer layers, in such a way that there are no tears in the layers and no increase in lattice defects.
In WO 2006/138378 A1, US 2006/0284247 A1 and US 7,420,226 B2, a bonded multi-layer wafer is used to integrate the silicon CMOS technology having III-V semiconductors on a wafer. The multi-layer wafer consists of a substrate wafer of a material having high thermal conductivity (for example SiC or diamond) having continuous layers provided thereon: a monocrystalline layer (for example (111)-orientated silicon), the III-V layer thereon (for example AlGaN/GaN), a passivation layer thereon (for example of nitride), and a silicon layer thereon. In a first region CMOS transistors are provided in the silicon layer, in a second region the silicon layer is etched away, and in the lower, exposed III-V layer a high electron mobility transistor (HEMT), for example, is provided.
US 2007 0105274 A1 (or US 2007 0105335 A1 and US 2007 0105256 A1) discloses the application of further monocrystalline semiconductor layers and insulator layers to a silicon substrate wafer. This multi-layer wafer is produced by bonding. Structures are also disclosed in which different semiconductor materials are located in different regions on the surface. An example is shown in FIG. 8 thereof, in which a multi-layer wafer on the surface consists of silicon regions and of monocrystalline semiconductor regions, which are mutually separated by insulator layers or shallow trench isolations. FIG. 9 thereof illustrates a fabrication method which initially takes a multi-layer wafer as a basis for a starting wafer, subsequently provides silicon components in a front region (but only by front-end steps, i.e. process steps up to the contact plane without metallisation), subsequently etches down to a crystalline semiconductor layer in a second region, and fills the resulting depression with an epitactically grown monocrystalline semiconductor layer. The front-end process steps for structures in the monocrystalline semiconductor layer and the back-end steps (i.e. fabrication and metallisation) are carried out in succession.
FIG. 8 of US 2007 0105274 A1 discloses a prior art which is incorporated herein as FIG. 1. In terms of structure, the disclosed semiconductor arrangement consists of two regions 18 and 19 and uses a multi-layer wafer as the starting material. The first region 18 consists of a monocrystalline silicon layer 14, which is deposited over an insulation layer 13. Below the insulation layer 13 there are a monocrystalline semiconductor layer 12, consisting of a germanium and/or silicon/germanium layer, and a silicon substrate layer 11. The second region 19 consists of a second monocrystalline semiconductor layer sequence 16 and 17, which is positioned at least on part of the monocrystalline semiconductor layer 12. The two regions 18 and 19 are laterally mutually insulated by an insulation layer 15 or by shallow trench isolations (oxide, nitride or a combination thereof).
Continuous layers on substrates, for example substrates consisting of monocrystalline silicon, having different expansion coefficients or structures from the substrate, such as are used in the known method, lead to difficulties in fabricating the layer arrangement, involving the resilient interlocking of the layer arrangement and the risk of structural defects occurring in the active monocrystalline semiconductor layers, and this leads to degradation of the characteristic data, to a yield reduction and to a reduction in the reliability of the components constructed in the damaged layers, quite apart from the increased process and material cost.